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ADI - Model ADH987S -Aerospace 3.3V Low Noise 1:9 Fanout Buffer DC – 4GHz
The ADH987S is a high-performance, low-noise 1-to-9 fanout buffer designed specifically for aerospace applications. Operating at a voltage of 3.3V, this device can support clock distribution with frequencies ranging from DC up to 4GHz. Its primary function is to generate square wave outputs with rapid rise and fall times, making it an excellent choice for applications that require precise timing and minimal noise interference. The ADH987S features 8 LVPECL outputs and a versatile CML output, which can have its power level adjusted in 3 dB increments. The inputs can be driven single-ended or differentially, and support multiple signal formats such as CML, LVDS, LVPECL, or CMOS, enhancing its compatibility. Additionally, the device features adjustable input impedance and the ability to enable or disable individual output stages for power conservation via hardware control pins or a serial-port interface. This combination of adjustable aspects and high precision makes the ADH987S ideal for use in sophisticated downstream circuits like mixers, ADCs/DACs, or SERDES devices, particularly where a wide clock network bandwidth is used.
he ADH987S 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with fast rise / fall times. The low skew outputs of the ADH987S, combined with its fast rise / fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs / DACs or SERDES devices. The noise floor is particularly important in these applications, when the clock network bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the ADH987S have a noise floor of -155 dBc/Hz.
The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.
Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.
- RF/µW
- Clock Distribution
- Clock Fanout
- LO Distribution
- Ultra Low Noise Floor: -155 dBc/Hz @ 2 GHz
- LVPECL, LVDS, CML & CMOS Compatible Inputs
- Up to 8 Differential or 16 Single-Ended LVPECL Outputs
- One Adjustable Power CML/RF Output
- Serial or Parallel Control, Hardware Chip-Enable
- Power-Down Current < 1 µA